The invention relates to a method of erasure for a non-volatile semiconductor memory device having a floating gate.
One of non-volatile semiconductor memory devices is an electrically erasable and programmable read only memory (EEPROM) having a floating gate. FIG. 1 illustrates a typical structure of the electrically erasable and programmable read only memory (EEPROM) having the floating gate. The electrically erasable and programmable read only memory (EEPROM) having the floating gate illustrated in FIG. 1 is an n-type channel metal oxide semiconductor field effect transistor (MOSFET).
In FIG. 1, the electrically erasable and programmable read only memory (EEPROM) device has a p-type silicon substrate 11. Drain and source diffusion layers 16 and 17 are formed in upper portions of the p-type silicon substrate 11 by using a diffusion method such as an ion-implantation technique with an n-type dopant of arsenic or phosphorus. The formation of the n-type drain and source diffusion layers 16 and 17 defines a channel region on the p-type silicon substrate 11. A tunneling oxide film 12 is formed on the channel region in the p-type silicon substrate 11. A floating gate 13 made of polycrystalline silicon is formed on the tunneling oxide film 12. An inter-layer insulator 14 is formed on the floating gate 13. A control gate 15 made of polycrystalline silicon is formed on the inter-layer insulator 14. Such gate structure is formed by using normal processes such as a thermal oxidation of silicon, a chemical vapor deposition, a photo-lithography and a dray etching.
The operations of the electrically erasable and programmable read only memory (EEPROM) device will be described. The programming is accomplished by a hot electron injection through a tunneling oxide film 12 into the floating gate 13 thereby making a threshold voltage of the MOSFET device high. In contrast, the erasure is accomplished by a Fowler-Nordheim tunneling of electrons from the floating gate 13 through the tunneling oxide film 12 thereby making the threshold voltage of the MOSFET device low.
In such non-volatile semiconductor memory device, and thus the electrically erasable and programmable read only memory (EEPROM) device, a threshold voltage after erasure is variable, which has been known in the art. A large variation or a broad distribution of the threshold voltage after erasure is one of the most considerable problems in performances possessed by such non-volatile semiconductor memory device and thus the electrically erasable and programmable read only memory (EEPROM) device. Namely, the large variation or the broad distribution of the threshold voltage after erasure makes performances of the non-volatile semiconductor memory device so unstable that high speed and precise memory actions of the device are no longer realized.
In recent years, the minimization of the device size is considerably improved. The minimization of the device size renders such problem in the large variation or the broad distribution of the threshold voltage after erasure considerable. Thus, such non-volatile semiconductor memory device are forced into being engaged with such problem in the broad distribution of the threshold voltage after erasure operation.
It is, therefore, required to suppress or prevent the non-volatile semiconductor memory device or the electrically erasable and programmable read only memory (EEPROM) device to exhibit such large variation or broad distribution of the threshold voltage after erasure.
One of methods of suppressing the non-volatile semiconductor memory device to exhibit such large variation or broad distribution of the threshold voltage after erasure is disclosed in Technical Digest of 1991 International Electron Device Meeting, pp-307-310. The erasure method will be described in detail with reference to FIGS. 1, 2 and 3.
The non-volatile semiconductor memory device has the same structure as illustrated in FIG. 1. The feature sizes of the device are as follows. The gate length is 0.6 (0.8) micrometers. The gate width is 0.6 micrometers. The thickness of the tunnel oxide film 12 is 10 nanometers. The thickness of the inter-layer insulator 14 is 22 nanometers.
The erasure method, to obtain tight distribution of the threshold voltage after erasure, utilizes an avalanche hot carrier injection through the tunneling oxide film 12 into the floating gate after erasure, and thus utilizes a Fowler-Nordheim tunneling of the hot carriers. As the device size of the MOSFET is minimized, an electric field in the device becomes high. A high electric field makes the energy of electrons high thereby electrons conduct as hot electrons. Further, such high electric field causes an impact ionization at a drain junction. The impact ionization generates an electron-hole pair thereby exhibiting the avalanche breakdown.
FIG. 2 illustrates characteristics of the gate current I.sub.g versus the floating gate voltage V.sub.fg for the electrically erasable and programmable read only memory (EEPROM) device having the floating gate 13. When the floating gate voltage V.sub.fg is higher than the drain-source voltage V.sub.DS, the avalanche hot carrier injection through the tunneling oxide film 12 into the floating gate 13 occurs. Thus, the high electric field causes the impact ionization in a space charge region at an junction interface between the n-type drain diffusion layer 16 and the channel region. The impact ionization generates electron-hole pairs in a space charge region at an junction interface between the n-type drain diffusion layer 16 and the channel region. This causes the avalanche breakdown so that the carriers, and thus hot electrons or hot holes are injected through the tunneling oxide film 12 into the floating gate 13 of the device.
When the floating gate voltage V.sub.fg is lower than a balance point floating gate voltage V.sub.fg *, a channel electron induced avalanche hot hole injection (CEIA-HH) so occurs that the hot holes are injected from the channel region through the tunneling oxide film 12 into the floating gate 13 of the device. In contrast, when the floating gate voltage V.sub.fg is higher than a balance point floating gate voltage V.sub.fg *, a channel electron induced avalanche hot electron injection (CEIA-HE) so occurs that the hot electrons are injected from the channel region through the tunneling oxide film 12 into the floating gate 13 of the device. When the floating gate voltage V.sub.fg is much higher than a balance point floating gate voltage V.sub.fg *, a channel hot electron injection (CHE) so occurs that the hot electrons are injected from the channel region through the tunneling oxide film 12 into the floating gate 13 of the device. When the floating gate voltage V.sub.fg is equal to a balance point floating gate voltage V.sub.fg *, the channel electron induced avalanche hot hole injection (CEIA-HH) and the channel electron induced avalanche hot electron injection (CEIA-HE) are in balance.
If the floating gate voltage V.sub.fg is lower than a balance point floating gate voltage V.sub.fg *, the hot holes are injected through the tunneling oxide film 12 into the floating gate 13 of the device thereby the floating gate voltage V.sub.fg is increased and approaches the balance point floating gate voltage V.sub.fg *. As a result, the gate current I.sub.g does not occur because the channel electron induced avalanche hot hole injection (CEIA-HH) and the channel electron induced avalanche hot electron injection (CEIA-HE) are in balance at the balance point floating gate voltage V.sub.fg *. In contrast, if the floating gate voltage V.sub.fg is higher than a balance point floating gate voltage V.sub.fg *, the hot electrons are injected through the tunneling oxide film 12 into the floating gate 13 of the device thereby the floating gate voltage V.sub.fg is lowered and also approaches the balance point floating gate voltage V.sub.fg *. As a result, the gate current I.sub.g also does not occur because the channel electron induced avalanche hot hole injection (CEIA-HH) and the channel electron induced avalanche hot electron injection (CEIA-HE) are in balance at the balance point floating gate voltage V.sub.fg *.
Finally, to realize the stable threshold voltage after erasure, such electrically erasable and programmable read only memory (EEPROM) device exhibits a self-convergence of the floating gate voltage V.sub.fg into the balance point floating gate voltage V.sub.fg * after erasure thereby realizing the stable threshold voltage after erasure.
The erasure operation of the electrically erasable and programmable read only memory (EEPROM) device will be described with reference to FIG. 3. FIG. 3 illustrates waveforms of voltage applied to respective electrodes of the control gate 15, the source 17 and drain 16 during data erasure operation. The erasure operation makes the n-type drain diffusion layer 16 remain at 0 V during the erasure operation. A negative pulse voltage is applied to the electrode the control gate 15 so that the control gate 15 takes -13 V for 0.1 seconds, after which the voltage takes 0 V. Concurrently, a positive pulse voltage is applied to the electrode of the n-type source diffusion layer 17 so that the n-type source diffusion layer 17 takes +5 V for 0.6 seconds, after which the voltage takes 0 V.
For a first time interval of 0.1 seconds, the control gate 15 takes a negative voltage of -13 V and the source diffusion layer 17 takes a positive voltage +5 V. In this first time interval of 0.1 V, the discharge of electrons from the floating gate 13 by the Fowler-Nordheim tunneling occurs thereby accomplishing the erasure. Further, the over-erasure is so accomplished that the floating gate 13 takes a higher voltage value than the balance point floating gate voltage V.sub.fg * of 2.0 V. After that, a second time interval of 0.5 seconds follows the first time interval of 0.1 second. For the second time interval, the control gate 15 takes 0 V and the voltage of the source diffusion layer 17 remains at the positive voltage +5 V for a remaining time interval of 0.5 seconds. The voltage application to the electrode of the source diffusion layer 17 causes the channel carrier induced avalanche hot electron injection (CEIA-HE) thereby hot electrons are injected through the tunneling oxide film 12 into the floating gate 13. This makes the floating gate voltage V.sub.fg converge into the stable point of the balance point floating gate voltage V.sub.fg *. As a result, the threshold voltage in connection with the control gate 15 also converges into a stable voltage value thereby making the distribution of the threshold voltage after erasure tight.
The above erasure method for the electrically erasable and programmable read only memory (EEPROM) device having the floating gate, however, provides the following disadvantages. As described above, the above erasure method utilizes the avalanche breakdown phenomenon caused at the space charge region at the junction interface of the n-type drain diffusion layer 16 for accomplishment of the erasure. Then, the space charge regions at the junction interface of the n-type drain and source diffusion layers 16 and 17 respectively exhibit the impact ionization phenomenon which generates electron-hole pairs. The avalanche phenomenon subjects a damage to the drain and source diffusion layers 16 and 17 and thus causes the junction breakdown between the drain and source diffusion layers 16 and 17 and the channel region.
In addition, the above self-convergence process for threshold voltage after erasure requires the bias between the drain and source diffusion layers 16 and 17 thereby a large power consumption is required.